In an active matrix type display, typically an active matrix type liquid crystal display, a thin film transistor (TFT) is formed in each pixel, and display information is stored on a pixel-by-pixel basis to display images. A TFT formed by using a polysilicon film which is fabricated by polycrystallization of an amorphous silicon film by laser annealing, with its mobility being raised to about 100 cm2/V·S is called a polysilicon TFT. Since a circuit configured of such polysilicon TFTs operates with signals of a few MHz to dozens of MHz, not only pixels but also a data driver circuit generating image signals and a driver circuit which has the scanning function of a gate driver circuit can be formed on the substrate of a liquid crystal display device or the like in the same process as the formation of the TFTs constituting the pixels.
The data driver circuit supplies an analog-signal voltage containing image signal information to a plurality of data lines. The data lines in this context are wires running in the vertical direction within the display screen of the image display device, and supply each pixel with an analog signal voltage.
The data driver circuit requires the following functions.
(1) A function to convert digital signals into analog voltages, namely the function of a DA converter. Where input image signals supplied from outside the image display device include many digital signals, it is preferable to build this function into the device.
(2) A function to distribute analog signal voltages. This is required because there are a plurality of data lines (usually as many as pixels in the horizontal direction of the frame).
FIG. 11 shows an example of configuration of a conventional data driver circuit. The data driver circuit comprises a decoder (DEC) 81, a shift register (SREG) 82 and a switch matrix 83. In the switch matrix 83, memory elements 84 each consisting of N-channel TFTs 85 and 86 and one capacitor 87 are arranged in a matrix form, and connected to one another by a plurality of decoded signal lines 88, a plurality of trigger lines 89, a plurality of reference voltage lines 90 and a plurality of output lines 91. The decoded signal lines 88 are connected to the output of the decoder 81, the trigger lines 89 to the shift register 82, the reference voltage lines 90 to external reference voltage lines Vref1 through Vrefx, and the output lines 91, to the data lines of the image display device.
The operation of the data driver circuit shown in FIG. 11 will be briefly described below. Digital image signals DSIG supplied from outside are decoded by the decoder 81, and supplied to the decoded signal lines 88. One of the decoded signal lines 88 relates to the entered digital image signal DSIG and takes on a sufficiently high voltage (hereinafter abbreviated to the H level) to turn ON the N-channel TFT, and the remaining ones take on a sufficiently low voltage (hereinafter abbreviated to the L level) to turn OFF the N-channel TFT. The shift register 82 successively raises one or another of the trigger lines 89 to the H level in synchronism with the input timings of the digital image signals DSIG.
On one column of the memory elements 84 connected to a trigger line 89 at the H level, as the TFT 85 is turned ON, the decoded signal on a decoded signal line 88 is latched into the capacitor 87. Out of the decoded signal lines 88, only one corresponding to the digital image signal DSIG is at the H level, and accordingly the capacitor 87 connected to that decode line samples the H level. Then, the TFT 86 to be connected to the capacitor 87 having sampled the H level is turned ON, and that TFT 86 selects one of the reference voltages Vref1 through Vrefx of the reference voltage lines 90 to be connected and outputs it to the output line 91. The reference voltage supplied to the output lines 91 is further fed to a data line of the image display device (not shown).
The operation described above causes the circuit of FIG. 11 (1) to convert digital image signals into corresponding voltage signals and (2) to distribute the voltage signals among the plurality of data lines, and is thereby enabled to perform its above-stated functions as a data driver circuit.
Examples of the circuit shown in FIG. 11 are also described in detail in Patent Document 1 and Patent Document 2. One of the features of the circuit shown in FIG. 11 is that, since the configuration requires merely the wiring of two lines per output in the longitudinal direction of the drawing, the circuit width per output can be narrowed, enabling the circuit to be applied to finer image display devices.
Patent Document 1: Japanese Patent Laid-Open No. 2003-005716
Patent Document 2: Japanese Patent Laid-Open No. 2004-085666